From powering data centers to controlling the Mars rover Perseverance, the world demands more of its semiconductors now than it did just a few years ago. As in the past, meeting these demands – and enabling technological leadership across the U.S. economy – will require new innovations, made possible by investments in semiconductor research and development (R&D). To be commercially useful, an innovation must traverse five phases of R&D before scaling to volume production. Each successive phase is increasingly challenging: a large portfolio of initial bets is required for 1-2 innovations to reach volume production.
R&D is a critical part of a virtuous cycle of innovation that supports U.S. technology leadership. Innovations yield superior technologies and products that, when used in commercial production, provide the funds needed to make massive investments in future R&D. To develop these innovations, the U.S. semiconductor industry invested $50 billion in R&D in 2021 alone. With Congressional anticipated approval of funding for the CHIPS (Creating Helpful Incentives to Produce Semiconductors) Act, the federal government is poised to make its largest investment in semiconductor R&D in decades. A national strategy for semiconductor R&D should target this investment toward critical gaps in the U.S. R&D ecosystem to revitalize the innovation pipeline, to align R&D with commercial priorities, and to strengthen U.S. technological competitiveness.
While the U.S. has world-class national labs, universities, and companies needed for innovations, its semiconductor R&D ecosystem faces challenges in directing investments, resourcing, facilitating collaboration, and bringing innovations to market (i.e., lab to fab gaps). If unaddressed, these challenges will limit the ecosystem’s effectiveness. Meanwhile, other regions are taking steps to mitigate these challenges and to improve the effectiveness of their own R&D ecosystems through initiatives like the EU’s own Chips Act and South Korea’s “K-Semiconductor Belt” initiative.
The long-expected funding of the CHIPS Act promises to amplify the scope and impact of existing U.S. semiconductor R&D organizations by establishing two new entities, the National Semiconductor Technology Center (NSTC) and the National Advanced Packaging Manufacturing Program (NAPMP). NSTC and NAPMP provide a critical framework, focus and funding for the U.S. R&D ecosystem, ensuring that the U.S. builds chipmaking capability in identifying paths to spur technology innovations that pave the way for sustaining long-term U.S. semiconductor leadership. The NSTC and NAPMP complement the strong CHIPS Act provisions designed to increase domestic semiconductor capacity.
The NSTC should be an industry-led entity, with the NAPMP closely aligned with the NSTC, to promote U.S. technological competitiveness most effectively. Based on our extensive consultations with industry leaders, the NSTC and NAPMP should partner widely across the semiconductor industry and bolster the U.S. R&D ecosystem’s capabilities through investments in five key areas.
The NSTC and NAPMP should serve to bridge the gap between early stage R&D and at-scale production. Both should strengthen the R&D ecosystem’s ability to conduct R&D and commercialize technologies that are 5 to 15 years from production, technologies for which regional leadership has yet to be determined. The NSTC and NAPMP can become hubs for aligning R&D efforts, both for industry and other agencies, allowing industry to participate in programs where it has interests, and enabling agencies to focus their own funds on their respective missions. While the efforts of both will be important, the commercial benefits of the NAPMP are likely to become evident sooner. The NSTC and NAPMP should augment, rather than replicate, existing organizations like Europe’s imec or the Semiconductor Research Corporation (SRC).
The NSTC and NAPMP should play an active role in expanding, upgrading, and providing access to institutions’ technology development capabilities where they align with R&D priorities. The two initiatives must neither spread funding evenly nor concentrate investments in a single technology or location. Rather, both must balance the benefits of a highly distributed network against the benefits of scale, based on technology needs. Specifically, it is critical that the NSTC and NAPMP use existing infrastructure where possible to leverage CHIPS funding and enable faster learnings by benefiting from available resources. This is especially important for piloting and prototyping to accelerate and broaden commercialization efforts. The primary support that the NSTC and NAPMP will provide for research efforts is the establishment of transition path for promising technologies through prototyping and scale-up.
The NSTC and NAPMP should support full-stack innovation by convening companies to solve complex technological problems that benefit from collaboration across the full computing stack and accelerate the development of technologies, tools, and methodologies. For example, creating next-generation data centers requires bringing together expertise in advanced materials, new computing architectures, packaging, software, and more. In particular, the NAPMP can convene technical experts to provide input to organizations like Institute of Electrical and Electronics Engineers (IEEE) and Joint Electron Device Engineering Council (JEDEC) when developing, for example, integration standards for heterogenous integration, chiplets, and other components of secure technologies.
The NSTC and NAPMP should promote a range of programs that expand the size and skills of the U.S. semiconductor R&D pipeline and workforce to defend and strengthen the U.S. R&D ecosystem and the economic competitiveness it underpins.
Without these efforts, the inadequate supply of highly skilled R&D workers – those in semiconductor design, manufacturing, and the other activities of the value chain-threatens to limit the pace of innovation.