CHIPS R&D funds will be allocated over multiple years and will be used to sustain various initiatives and programs, operate facilities, support funding opportunities, conduct research projects, promote workforce development, and more.

Background

The NAPMP is led by Director Dr. Dev Palmer and is seeking to invest in the below R&D areas, alongside an advanced packaging piloting facility to be co-located with the NSTC prototyping facility

Learn more at CHIPS.gov.

Funding Opportunities

• NOFO #1 - Materials & Substrates - $300 million - Awardees
  • Arizona State University
  • Applied Materials
  • Absolics
• NOFO #2 - Remaining 5 R&D areas - $1.6 billion
  • Equipment, Tools, Processes, and Process Integration - $450 million
  • Power Delivery and Thermal Management - $250 million
  • Connector Technology, Including Photonics and Radio Frequency (RF) - $250 million
  • Chiplets Ecosystem - $300 million
  • Co-design/Electronic Design Automation (EDA) - $250 million

Background

Director Dr. Paul Hale leads the CHIPS Metrology Program, which has various ongoing research activities and is leading NIST semiconductor and microelectronics metrology efforts centered around 7 grand challenges. The Program also features a Metrology Community of Practice.

CHIPS Metrology Grand Challenges – Metrology Gaps in the Semiconductor Ecosystem

1. Metrology for Materials Purity, Properties, and Provenance
2. Advanced Metrology for Future Microelectronics Manufacturing
3. Enabling Metrology for Integrating Components in Advanced Packaging
4. Modeling and Simulating Semiconductor Materials, Designs, and Components
5. ​​​​​​​​​​​​​​Modeling and Simulating Semiconductor Manufacturing Processes
6. Standardizing New Materials, Processes, and Equipment for Microelectronics
7. Metrology to Enhance Security and Provenance of Microelectronic-based Components and Products

Learn more at CHIPS.gov.

Funding Opportunities

• Ongoing Projects and Programs
• Small Business Innovation Research (SBIR) - $54 million (Phase 1 - $4.8 million) - Awardees
  • Sigray Inc. – Concord, CA
  • Photon Spot, Inc. – Monrovia, CA
  • HighRI Optics, Inc – Oakland, CA
  • Direct Electron LP – Rancho Bernardo, CA
  • ReconRF – San Diego, CA
  • Photothermal Spectroscopy Corporation – Santa Barbara, CA
  • PrimeNano Inc. – Santa Clara, CA
  • Tech-X Corporation – Boulder, CO
  • Vapor Cell Technologies – Boulder, CO
  • Octave Photonics – Louisville, CO
  • Virtual EM, Inc – Ann Arbor, MI
  • The Provenance Chain Network – Portland, OR
  • Tiptek LLC – West Chester, PA
  • Exigent Solutions – Frisco, TX
  • Laser Thermal Analysis, Inc. – Charlottesville, VA
  • Hummingbird Scientific – Olympia, WA
  • Steam Instruments, Inc. – Madison, WI

Background

Led by Director Dr. Eric Forsythe, CRDO launched a NOFO for up to $285 million the establishment of a Manufacturing USA Institute focused on digital twins for the semiconductor industry. Digital twins are virtual models that mimic the structure, context, and behavior of a physical counterpart.

The Semiconductor Research Corporation (SRC) was selected to establish the Semiconductor Manufacturing and Advanced Research with Twins USA, or SMART USA, Institute to focus on efforts to more rapidly develop, validate, and use digital twins to improve domestic semiconductor design, manufacturing, advanced packaging, assembly, and test processes. The institute will be supported by $1 billion in funding, including $285 million from the Department of Commerce. The CHIPS Manufacturing USA Institute will join an existing network of seventeen Institutes.

Learn more at CHIPS.gov.

CHIPS Digital Twins Manufacturing USA Institute

The objectives of the Institute include:

• Convene stakeholders across the semiconductor production ecosystem
• Improve the state of the art in manufacturing-relevant digital twins
• Significantly reduce cost for U.S. chip development and manufacturing
• Improve development cycle times of semiconductor product innovation
• Advance digital twin-enabled curricula for training a domestic semiconductor workforce
• Create a digital twin marketplace for industry to access digital models

Background

The ME Commons awarded $269 million to 33 projects in 27 states. Additional information about the projects is forthcoming, with preliminary detail below

• Quantum: 4 projects, $32 million
• Secure edge computing: 4 projects, $25 million
• 5G/6G: 5 projects, $42 million
• Electromagnetic warfare: 6 projects, $51 million
• Commercial leap-ahead: 7 projects, $38 million
• Artificial intelligence, 7 projects, $42 million
• Cross-Hub Enablement Solution (CHES) award: $39 million.

The goal of the Microelectronics Commons programs is to address the "valley of death" and facilitate the lab-to-fab transition for microelectronics research with defense applications. The ME Commons is led by Dr. Dev Shenoy at DOD and Stephanie Lin at NSTXL.

• "Unique Commons Hub Initiatives Nurture Workforce Development" - July 1 Blog post
• Call for Topics released on June 24, 2024 - Topics due July 24, 2024. Topic submissions will only be accepted from the eight Microelectronics Commons Hubs.
  • CFT Technical Guidance
• ME Commons Request for Projects November 2023 - webinar and resources
• ME Commons Annual Meeting October 2023 - resources
• The Department of Defense selected 8 hubs to lead its ME Commons programs in Sept. 2023 (right)
• Overview Presentation October 2022 - slides

Learn more at MicroelectronicsCommons.org and CTO.mil.